1. Field of the Invention
Generally, the present disclosure relates to the fabrication of highly sophisticated integrated circuits including transistor elements that comprise a high-k metal gate electrode structure formed in an early process stage.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a great number of circuit elements to be formed on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Currently, a plurality of process technologies are practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a planar transistor architecture, on the distance between the source and drain regions, which is also referred to as channel length.
Presently, the vast majority of integrated circuits are formed on the basis of silicon due to its substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the past 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and thus allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a base material for gate insulation layers that separate the gate electrode, frequently comprised of polysilicon, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by, among other things, the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length for a planar transistor configuration requires an increased capacitive coupling in combination with sophisticated lateral and vertical dopant profiles in the drain and source regions to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel length. Aggressively scaled planar transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current due to the required enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly reduced to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although usage of high speed transistor elements having an extremely short channel may typically be restricted to high speed applications, whereas transistor elements with a longer channel may be used for less critical applications, such as storage transistor elements, the relatively high leakage current caused by the direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may no longer be compatible with requirements for many types of circuits.
For this reason, new strategies have been developed in overcoming the limitations imposed by high leakage currents of extremely thin silicon oxide based gate insulation layers. One very promising approach is the replacement of the conventional dielectric materials, at least partially, by dielectric materials having a dielectric constant that is significantly greater than the dielectric constant of silicon dioxide based materials. For example, dielectric materials, also referred to as high-k dielectric materials, with a dielectric constant of 10.0 and significantly higher may be used, for instance in the form of hafnium oxide, zirconium oxide and the like. In addition to providing a high-k dielectric material in the gate insulation layers, appropriate metal-containing materials may also have to be incorporated since the required work function values for P-channel transistors and N-channel transistors may not be obtained on the basis of standard polysilicon gate materials. To this end, appropriate metal-containing materials may be provided so as to cover the sensitive high-k dielectric materials and act as a source for incorporating an appropriate metal species, such as lanthanum, aluminum and the like, in order to appropriately adjust the work function for N-channel transistors and P-channel transistors, respectively. Furthermore, due to the presence of a metal-containing conductive material, the generation of a depletion zone, as may typically occur in polysiliconbased electrode materials, may be substantially avoided. The process of fabricating a sophisticated gate electrode structure on the basis of a high-k dielectric material may require a moderately complex process sequence due to, for instance, the adjustment of an appropriate work function for the transistors of different conductivity type and the fact that high-k dielectric materials may typically be very sensitive when exposed to certain process conditions, such as high temperatures in the presence of oxygen and the like. Therefore, different approaches have been developed, such as providing the high-k dielectric material at an early manufacturing stage and processing the semiconductor devices with a high degree of compatibility with standard process techniques, wherein the typical electrode material polysilicon may be replaced in a very advanced manufacturing stage with appropriate metals for adjusting the work function of the different transistors and for providing a highly conductive electrode metal. While this approach may provide superior uniformity of the work function and thus of the threshold voltage of the transistors, since the actual adjustment of the work function may be accomplished after any high temperature processes, a complex process sequence for providing the different work function metals in combination with the electrode metal may be required. In other very promising approaches, the sophisticated gate electrode structures may be formed in an early manufacturing stage, while the further processing may be based on the plurality of well-established process strategies. In this case, the high-k dielectric material and any metal species for adjusting the work function may be provided prior to or upon patterning the gate electrode stack, which may comprise well-established materials, such as silicon or silicon/germanium, thereby enabling the further processing on the basis of well-established process techniques. On the other hand, the gate electrode stack and, in particular, the sensitive high-k dielectric materials, in combination with any metal-containing cap layers, may remain reliably confined by appropriate materials throughout the entire processing of the semiconductor device.
Although the approach of providing a sophisticated high-k metal gate electrode structure with an appropriately set work function in an early manufacturing stage may be a very promising approach, it turns out that conventional strategies may suffer from a plurality of process non-uniformities, as will be explained in more detail with reference to FIGS. 1a-1b. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100, comprising a substrate 101, such as a silicon substrate, and a silicon-based semiconductor layer 102, which may represent a portion of a crystalline silicon material of the substrate 101, when a “bulk” configuration is provided. In the manufacturing stage shown, the semiconductor device 100 further comprises transistors 150A, 150B in an early manufacturing stage, wherein the transistors 150A, 150B are formed in and above respective active regions 102A and 102B. An active region is to be understood as a semiconductor region in the layer 102 in which the PN junctions for one or more transistors are to be formed. In the example shown, the transistor 150A represents a P-channel transistor, while the transistor 150B represents an N-channel transistor. The transistors 150A, 150B comprise gate electrode structures 160A, 160B, respectively. In this manufacturing stage, the gate electrode structures 160A, 160B comprise a gate dielectric material 161, which may be referred to as a high-k dielectric gate insulation layer, since at least a portion of the gate dielectric material 161 may comprise a material or layer providing a dielectric constant of approximately 10.0 or higher. For example, hafnium oxide based materials, zirconium oxide based materials and the like may frequently be used as a high-k dielectric material portion in sophisticated gate electrode structures, possibly in combination with “conventional” gate dielectrics, such as silicon oxynitride and the like. Furthermore, the gate electrode structures 160A, 160B comprise an electrode material 163, for instance in the form of a silicon material, such as amorphous or polycrystalline silicon material. Furthermore, a dielectric cap layer 164, typically comprised of silicon nitride, possibly in combination with silicon dioxide, is formed on top of the electrode material 163. The gate electrode structure 160A further comprises a conductive cap material 162A formed on the gate dielectric material 161 and comprising an appropriate work function adjusting metal species, such as aluminum, thereby obtaining the desired electronic characteristics. It should be appreciated that, in some approaches, the active region 102A may comprise an appropriate “channel” semiconductor material 102C in order to obtain a desired band gap offset, which, in combination with materials 161 and 162A, results in the desired threshold voltage of the transistor 150A. For example, the material 102C is provided as a silicon/germanium mixture or alloy with a specified thickness and germanium concentration as required for adapting the band gap offset for the transistor 150A. Similarly, the gate electrode structure 160B comprises a conductive cap layer 162B, which in turn contains an appropriate work function adjusting metal species, such as lanthanum and the like.
Additionally, since the stability of the work function and thus threshold voltage of the transistors 150A, 150B strongly depends on the integrity of the materials 161 and 162A, 162B, a spacer or liner material 165 is provided so as to confine the sidewalls of the gate electrode structures 160A, 160B. For this purpose, typically, silicon nitride material is used, which may be formed on the basis of sophisticated deposition techniques, such as thermally activated chemical vapor deposition (CVD), plasma assisted CVD techniques or any combination thereof, in which a highly conformal and dense silicon nitride material is obtained. Furthermore, in this manufacturing stage, a sacrificial spacer 103, such as an oxide spacer and the like, is formed on the protective spacer 165.
Typically, the semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of the following processes. After providing the active regions 102A, 102B, which is typically accomplished by forming isolation structures (not shown) so as to laterally delineate respective semiconductor regions in the layer 102, followed by the incorporation of an appropriate dopant species in order to adjust the basic transistor characteristics, materials for the gate dielectric material 161 and the conductive cap layers 162A, 162B are formed. For this purpose, well-established manufacturing techniques may be used. For example, the gate dielectric material 161 may be provided in the form of a silicon oxynitride material, followed by a high-k dielectric material, such as hafnium oxide. Thereafter, one or more materials are deposited, such as titanium nitride, in combination with an appropriate work function species, such as aluminum. Depending on the process strategy, appropriate materials may also be deposited for the gate electrode structure 160B, while an unwanted portion of any previously-provided materials may be removed on the basis of well-established lithography and patterning strategies. Furthermore, a thermal stabilization of these materials may be accomplished in this manufacturing stage, if required, so as to diffuse the metal species into the gate dielectric material 161. If required, the metal materials may be removed and an electrode material, such as titanium nitride and the like, may be commonly applied for the gate electrode structures 160A, 160B. Next, the silicon material 163 is deposited, for instance, by low pressure CVD and the like, followed by the deposition of the dielectric cap material 164. Furthermore, additional materials, such as hard mask materials, anti-reflective coating (ARC) materials and the like, may be provided as required. Thereafter, a complex lithography and etch sequence is performed, thereby patterning the gate electrode structures 160A, 160B so as to obtain the desired gate length in accordance with the design rules. For example, the gate length, i.e., in FIG. 1a, the horizontal extension of, for example, the conductive cap materials 162A, 162B, may be 40 nm and less.
Thereafter, the protective sidewall spacer structure 165 is formed, for instance, by depositing a silicon nitride material and etching the same on the basis of a plasma assisted etch process. Consequently, during any subsequent processes, such as cleaning processes and the like, the materials 161 and 162A, 162B are confined by the spacer 165. In order to avoid undue variations of the electronic characteristics of the gate electrode structures 160A, 160B, at least the materials 161 and 162A, 162B have to be confined by the spacer 165 throughout the entire process flow, since, typically, many wet chemical etch processes on the basis of sulfuric acid, hydrofluoric acid and the like have to be performed, which may, upon contacting, for instance, the material 162A, 162B, remove a significant portion, thereby causing corresponding device failures.
Furthermore, in any advanced manufacturing stage, the sacrificial spacers 103 may be formed by depositing, for instance, a silicon dioxide material and etching this material on the basis of a plasma assisted etch recipe. The sacrificial spacers 103 are provided so as to protect the spacers 165 during an etch process for removing the dielectric cap material 164, which has been used during the patterning of the gate electrode structures 160A, 160B and which may also be used in other process sequences, in which a reliable confinement of the materials 163, 162A, 162B and 161 of the gate electrode structures 160A, 160B is required.
Due to the previous processing and in particular due to the spacer etch processes for forming the sacrificial spacer 103, a certain degree of recessing, as indicated by 102R, may occur in the active regions 102A, 102B. Moreover, the degree of recessing 102R may be even further increased by removing the dielectric cap layer 164 on the basis of hot phosphoric acid, while the sacrificial spacers 103 may reliably protect the spacers 165. Next, the sacrificial spacers 103 are removed, for instance, on the basis of hydrofluoric acid, substantially without affecting the spacers 165.
FIG. 1b schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As illustrated, an offset spacer 166 is formed on the protective spacer element 165 in order to appropriately adjust a lateral offset of implantation species to be incorporated into the active regions 102A, 102B. For this purpose, the gate electrode structures 160A, 160B, in which the dielectric cap layer 164 has been removed, may act as an implantation mask. For instance, an implantation mask may cover the gate electrode structure 160B and the active region 102B, for instance by providing a resist mask (not shown), while the transistor 150A is exposed to an ion implantation process sequence 104A in order to introduce drain and source dopant species for forming drain and source extension regions and also for incorporating a counter doping species, which is typically required for forming halo regions, thereby appropriately adjusting the critical dopant profile, for instance in view of adjusting the off current of the transistors. Typically, the counter doping species is to be positioned below the drain and source extension regions and thus requires a higher implantation energy compared to the drain and source extension regions, wherein, however, the ion blocking effect of the gate electrode structures 160A, 160B may be restricted by height and the length of the electrode material 163. In order to avoid undue penetration of critical areas, such as the materials 162A, 162B by the halo dopant species, the corresponding implantation energy has to be restricted accordingly in order to avoid undue threshold voltage shifts. Furthermore, the significant degree of recessing 102R may also contribute to a less efficient overall dopant profile in the vicinity of the channel regions 153 and may result in a significant reduction of performance of the transistors 150A, 150B, which may particularly affect semiconductor devices designed for low power applications.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.